This invention relates to a semiconductor device, and more particularly it relates to an insulated gate field effect transistor semiconductor device providing protection against gate rupture and oxide breakdown of MOS devices and integrated circuits.
Insulated gate MOS transistors are typically formed with a thin oxide layer insulating a control gate electrode from the transistor channel over which it lies and controls. Such MOS devices and integrated circuit elements have an extremely high input impedance which makes them particularly sensitive to the accumulation of static charges. Such charges may typically be induced during fabrication, packaging, testing or installation of the integrated circuit. The static charges may reach high voltages which are sufficient to rupture the thin oxide layer resulting in consequent device failure.
Consequently, a common practice has been to provide MOS integrated circuits with protective devices and structures to clamp incoming voltages to levels below the gate oxide rupture or breakdown voltage. Typically those devices were characterized as zener-like diodes and/or series resistors which were often fabricated as a part of the integrated circuit both in combination and separately.
With V-groove MOS structures, the problem of gate oxide breakdown has been acute in that the oxide breakdown voltage of such circuit elements is substantially below the junction breakdown voltage of diodes heretofore utilized to provide input gate protection. The geometric configuration of the V-groove MOS transistor structure results in the gate electrode having either a point or an edge at the bottom of the V-groove. This point or edge has proven to be the cause of the lower breakdown voltage of the underlying thin insulating oxide layers.
Consequently, conventional MOS input gate protection diodes have afforded no protection for preventing gate oxide breakdown in V-groove MOS devices. Therefore, strict handling procedures with thorough grounding of equipment and careful selection of clothing and material have been essential for personnel handling such MOS devices and have not always prevented device ruination on account of gate rupture.
On the other hand, the inclusion of high resistance input resistors to protect V-groove MOS gate oxides has not been a satisfactory solution as such resistors have resulted in undue speed losses which have cancelled gains otherwise available with the V-groove MOS transistor technology, as more fully explained in the assignee's U.S. Pat. No. 3,924,265 issued Dec. 2, l975.